1. Field of the Invention
The present invention generally relates to a parallel test circuit for semiconductor memory devices. More particularly, it relates to a multiple bit parallel test circuit for semiconductor memory devices which is an improved lay-out suitable for memory test performance for semiconductor devices of high integration.
The present application is based on Korean Application No. 55738/1995.
2. Description of the Related Art
In recent years, semiconductor memory devices, particularly, dynamic random access memory devices, have dramatically increased in density and accuracy. The chip size has become large, and test processing time for checking the memory devices has increased thereby. Malfunction of memory cells commonly results from a single-bit failure, since accessing the bits one by one in order to test for defects prolongs the test processing time and raises testing costs. To meet the needs of a test circuit which is able to check for failures in chips within a short period of time, a multiple-bit parallel test circuit has been proposed.
In the operation of this multiple bit parallel test circuit, the same data is written into all the memory cells, then the data stored in each memory cell is read out during one access cycle. The multiple-bit parallel test circuit performs a comparison operation with the read data. When the data does not match the value which was read into the memory cells in the previous operation, the multiple-bit parallel test circuit interprets this as a "failure".
FIG. 1 depicts the data path of a conventional parallel test circuit in which a one/zero/hi-Z test circuit is added to each one/zero test circuit as an option.
In this parallel test circuit, multiple bits are accessed simultaneously during a parallel test mode. Parallel test circuits are classified into two types: the one/zero test circuit S2 in which an output of its data output buffer, "0" or "1" is representative of "Pass" or "Fail", and a one/zero/hi-Z test circuit S3 in which a data pattern can be detected when the output of the data output buffer in the parallel test circuit is "0" or "1". In this type of test, high-impedance data ("hi-Z") is produced when the output of the data output buffer is defective. Neither of these two circuits is a standard one, and these two circuits are employed according to circumstances. In the presently-available test technique, a hi-Z test circuit is added to each one/zero test circuit as an option.
FIG. 1 is a schematic representation of a memory array which includes multiple memory banks. Each memory bank is divided into a predetermined number of memory blocks. The memory array of FIG. 1 includes two memory banks each having four memory blocks. Each memory block includes a predetermined number of data lines (DO lines), to which a DO line multiplexer S1 (DO MUX) is electrically connected. A one/zero test circuit S2 is connected in common with the DO lines as well as a one/zero/hi-Z test circuit S3. Each output terminal of the DO MUIX S1, the one/zero test circuit S2 and the one/zero/hi-Z test circuit S3 is connected is in common to a predetermined number of first data buses (FDB).
Since there arm four memory blocks in each memory bank of FIG. 1, the number of the FDBs is four. The FDBs are electrically connected to the input terminals of a first data bus comparator S4 (FDB comparator). The FDB comparator S4, has an output terminal connected to a second data bus (SDB), and the SDB and SDB are connected to a merged data bus (MDB) via NAND gate 1. The MDB is connected at one end to the input terminal of a data bus multiplexer S5 (DB MUX). The DB MUX S5 has an output terminal DB1 connected to the input terminal of a data output buffer DOUT S6. The lower part of FIG. 1's circuit is of construction similar to the above-described upper part.
FIGS. 2 to 7 are circuit diagrams respectively of: an enable clock generating circuit for FIG. 1's comparator, an enable signal generating circuit for the comparator, the comparators S2 and S3, the FDB comparator, the MDB circuit, and the DB multiplexer. Their circuitry is well known to those skilled in this art.
During normal mode, data of the DO lines are sent to the FDBs via the DO MUX S1, and are sent to the DOUT S6 through the SDB and MDB. The data is transferred to the DOUT S6 and is transmitted to outside.
When the one/zero/Hi-Z test circuit is added to the basic one/zero test commit during the parallel test mode, the data of the DO lines is first pressed by the comparators S2 and S3, and the output data of the comparators S2 and S3 are conveyed to the FDBs. The FDB comparator S4, performs the second comparison with respect to the data of the FDBs. The output data of the FDB comparator S4 is conveyed to the SDB. The data of the SDB is conveyed to the MDB via the NAND gate 1, and is then transferred to outside by way of the DB MUX S5 and DOUT S6. Data stored in the memory arrays of the above process undergo a test through the steps of comparison. The operation of the comparators may be simply carried out by using the exclusive OR circuits shown in FIG. 4 or 5.
During a conventional parallel test, a change in the output data is by the optional circuit.
The output of FIG. 2's enable clock generating circuit is enabled to a "high" level when the external test enable signal PFTE, indicative of the parallel test mode, and the column (Y) enable PYE signal are synchronized with the row address strobe signal RASB, and attain a "high" level each, and an output PWR of a WEB buffer indicative of a read mode and an output PC of a CASB buffer that buffers a column address strobe signal CASB attain a "low" level and a "high" level respectively.
FIG. 3 is a circuit diagram of the enable signal generating circuit of FIG. 1's comparator S2 or S3.
Once the multiple bit parallel test is carried out, in one/zero mode, a signal PFCOMD is enabled to a "high" level. During the one/zero/Hi-Z mode, as an enable signal PHLZE goes "high", a signal PFCOMDP is enabled to a "high" level. The DO MUX S1, one/zero comparator S2 and one/zero/Hi-Z comparator S3 are necessary for each DO line. Each one of the DO lines requires FIG. 4's circuitry. The path from the first part of the data path to the data output buffer should be modified as circumstances require, which makes the circuit lay-out and circuit control difficult. The data processed through the comparators is conveyed to the FDBs. The FDB comparator performs the second comparison with respect to the data of the FDBs.
According to the conventional parallel test circuit, in order to perform the one/zero test or one/zero/Hi-Z test without error, comparators for each mode are connected to appropriate memory blocks. In this configuration, the data buses of the comparators have complicated connections to increase their lay-out in size and the controlling process becomes complicated.